HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.7.8
Read followed by Precharge on the same Bank
0
1
2
3
6
7
8
9
10
CLK#
CLK
Com.
Addr.
RD
N/D
PRE
N/D
N/D
N/D
N/D
N/D
N/D
B / C
CAS latency = 7
RDQS
DQ
D0
D1
D2
D3
CAS latency = 8
RDQS
DQ
D0
D1
D2
D3
tRP
B / C: Bank / Column address
RD: READ
PRE: PRECHARGE
Dx: Data from B / C
N/D: NOP or Deselect
Don't Care
Com.: Command
Addr.: Address B / C
DQs : Terminations off
RDQS : Not driven
Figure 44 Read followed by Precharge on the same bank
1. tRAS requirement must also be met before issuing PRE command
2. RD and PRE commands are applied to the same bank.
3. Shown with nominal tAC and tDQSQ
4. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS.
Data Sheet
63
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
