HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.7.3
Consecutive Read Bursts
Gapless Bursts
4.7.3.1
0
1
2
3
6
7
8
9
10
11
12
13
CLK#
CLK
Com.
RD
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/Cx
B/Cy
CAS latency = 7
RDQS
DQ
Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
CAS latency = 8
RDQS
DQ
Dx0
Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
B / Cx: Bank / Column address x
B / Cy: Bank / Column address y
RD:
READ
N/D: NOP or Deselect
Dx#:
Dy#:
Data from B / Cx
Data from B / Cy
Don't Care
DQs : Terminations off
RDQS : Not driven
Com.: Command
Addr.: Address B / C
Figure 39 Gapless Consecutive Read Bursts
1. The second RD command may be either for the same bank or another bank.
2. Shown with nominal tAC and tDQSQ
.
3. Example applies only when READ commands are issued to same device.
4. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS.
5. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data.
Data Sheet
58
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
