HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.8.2
DTERDIS followed by READ
0
1
2
5
6
7
8
9
12
13
14
15
16
17
CLK#
CLK
Com.
Addr.
DTD
N/D
N/D
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B/Cx
CAS latency = 7
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Com.
Addr.
DTD
N/D
N/D
N/D
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B/Cx
CAS latency = 7
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Don't Care
Com.: Command
Addr.: Address B / C
B / Cx: Bank / Column address x
RD: READ
DQs : Terminations off
RDQS : Not driven
DTD: DTERDIS
N/D:
Dx#:
NOP or Deselect
Data from B / Cx
Figure 48 DTERDIS Command followed by READ
1. At least 3 NOPs are required between a DTERDIS command and a READ command in order to avoid
contention on the RDQS bus in a 2 rank system.
2. CAS Latency 7 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4
clocks.
Data Sheet
66
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
