HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.7.2
Read - Basic Sequence
0
1
2
3
6
7
8
9
10
11
CLK#
CLK
Com.
Addr.
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B / C
CAS latency = 7
RDQS
DQ
D0
D1
D2
D3
CAS latency = 8
RDQS
DQ
D0
D1
D2
D3
RD:
READ
B / C: Bank / Column address
Dx: Data from B / C
Com.: Command
N/D: Nop or Deselect
Don't Care
Addr.: Address B / C
DQs : Terminations off
RDQS : Not driven
Figure 38 Read Burst
1. Shown with nominal tAC and tDQSQ
.
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS.
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data.
Data Sheet
57
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
