HYB18H512321AF
512-Mbit GDDR3
Functional Description
tCH
tCL
tCK
tHP
CLK#
CLK
tDQSCK
RDQS
Preamble
tRPRE
Postamble
tRPST
DQ (first data valid)
DQ (last data valid)
D0
D1
D2
D3
D0
D1
D2
D3
tAC
All DQs collectively
D0
tDQSQ
tQH
D1
D2
tDQSQ
D3
data
valid
window
Don't Care
Hi-Z : Not driven
by DDRIII SGRAM
tQHS
tLZ
tHZ
Figure 37 Basic Read Burst Timing
1. The GDDR3 SGRAM switches off the DQ
2. The GDDR3 SGRAM drives the data bus HIGH one
cycle after the last data driven on the bus before
switching the termination on again.
terminations one cycle before data appears on the
bus and drives the data bus HIGH.
Data Sheet
56
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
