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HYB18H512321AFL20 参数 Datasheet PDF下载

HYB18H512321AFL20图片预览
型号: HYB18H512321AFL20
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 16MX32, 0.35ns, CMOS, PBGA136]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 100 页 / 1884 K
品牌: QIMONDA [ QIMONDA AG ]
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HYB18H512321AF  
512-Mbit GDDR3  
Boundary Scan  
Table 10  
Scan Pin Description  
PACKAGE SYMBOL NORMAL TYPE  
DESCRIPTION  
BALL  
FUNCTION  
V-9  
SSH  
SCK  
RES  
Input  
Input  
Scan Shift: Capture the data input from the pad at logic LOW  
and shift the data on the chain at logic HIGH.  
F-9  
CS  
Scan Clock: Not a true clock, could be a single pulse or series  
of pulses. All scan inputs will be referenced to rising edge of the  
scan clock  
D-2  
V-4  
SOUT  
SEN  
WDQS0  
SEN  
Output Scan Output  
Input  
Scan Enable: Logic HIGH enables the device into scan mode  
and will be disabled at logic LOW. Must be tied to GND when not  
in use.  
A-9  
SOE  
MF  
Input  
Scan Output Enable: Enables (registered LOW) and disables  
(registered HIGH) SOUT data. This pin will be tied to VDD or GND  
through a resistor (typically 1Kfor normal operation. Tester  
needs to overdrive this pin to guarantee the required input logic  
level in scan mode.  
Notes  
1. When SEN is asserted, no commands are to be executed by the GDDR3. This applies both to user commands  
and manufacturing commands which may exist while RES is deasserted.  
2. The Scan Function can be used right after bringing up VDD / VDDQ of the device. No initialization sequence of  
the device is required. After leaving the Scan Function it is required to run through the complete initialization  
sequence.  
3. In Scan Mode all terminations for CMD/ADD and DQ, DM, RDQS and WDQS are switched off.  
4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE’s should  
be provided to top and bottom devices to access the scanned output. When either of the devices is in scan  
mode, SOE for the other device which is not in a scan will be disabled.  
Table 11  
Scan DC Electrical Characteristics and Operating Conditions  
PARAMETER/CONDITION  
Input High (Logic 1) Voltage  
Input Low (Logic 0) Voltage -  
1) The parameter applies only when SEN is asserted.  
2) All voltages referenced to GND.  
SYMBOL  
VIH(DC)  
VIL(DC)  
MIN  
MAX  
VREF-0.15 V  
UNITS  
NOTES  
1)2)  
V
REF+0.15  
1) 2)  
Data Sheet  
25  
Rev. 1.73, 2005-08  
05122004-B1L1-JEN8  
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