HYB18H512321AF
512-Mbit GDDR3
Functional Description
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
Com
WR
B/C
DES
DES
DES
DES
DES
PRE
B
DES
DES
DES
.
Addr.
WR
B/C
DES
DES
DES
DES
DES
DES
PRE
B
DES
DES
WL = 3
tWR
tRP
WDQS
DQ
D0
D1
D2
D3
WR
B/C
DES
DES
DES
DES
DES
DES
DES
PRE
B
DES
tWR
tRP
WL = 4
WDQS
DQ
D0
D1
D2
D3
B / C: Bank / Column address
Com.: Command
Don't Care
WR:
PRE:
Dx#:
Dy#:
WRITE
Addr.: Address B / C
PRECHARGE
Data to B / Cx
Data to B / Cy
WL:
Write Latency
DES: Deselect
Figure 62 Write followed by Precharge
4.14.4
Reads (RD) in DLL off mode
Definition of read latency in DLL off mode is different from DLL on mode. Since in DLL off mode the read data is
not synchronized to the CLK, the internal access time to the memory array becomes visible. Read data in DLL off
mode appears on the I/O balls after (CL - 1) + tAC. CL is the value for the read latency which is set in the Mode
Register.
Data Sheet
76
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
