HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.13
Power-Down
defined one clock after the rising edge of the Write
Postamble.
For Read with Autoprecharge and Write with
Autoprecharge, the internal Autoprecharge must be
completed before entering Power-Down.
CLK#
CLK
CKE
Power-Down is entered when CKE is registered LOW.
(No access can be in progress. "Access" means as well
READ or WRITE to a second memory sharing the data
bus in a dual rank system.) If Power-Down occurs when
all banks are idle, this mode is referred to as Precharge
Power-Down; if Power-Down occurs when there is a
row active in any bank, this mode is referred to as
Active Power-Down. Entering power-down deactivates
the input and output buffers, excluding CLK, CLK and
CKE. For maximum power saving, the user has the
option of disabling the DLL prior to entering power-
down. In that case the DLL must be enabled and reset
after exiting power-down, and 1000 cycles must occur
before a READ command can be issued.
In Power-Down mode, CKE low and a stable clock
signal must be maintained at the inputs of the GDDR3
Graphics RAM, all the other input signals are “Don’t
Care”. Power down duration is limited by the refresh
requirements of the device.
The Power-Down state is synchronously exited when
CKE is registered HIGH (along with a NOP or DESEL
command). A valid executable command may be
applied tXPN later.
1
2
CS#
RAS#
CAS#
WE#
A0-A11
1: DESEL, 2: NOP
Don't Care
BA0-BA2
Figure 58 Power Down Command
The requires CKE to be active at all times an access
is in progress : From the issuing of a READ or WRITE
command until completion of the burst. For READs, a
burst completion is defined after the rising edge of the
Read Postamble. For Writes, a burst completion is
CLK#
CLK
N / D
N / D
N / D
N / D
A.C.
A.C.
Comm.
CKE
tIS
tXPN
N / D: NOP or DESELECT
Command
Power-Down
Mode Entry
Power-Down
Mode Exit
A.C.:
Any Command
Don't Care
Figure 59 Power-Down Mode
Data Sheet
73
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
