HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.14.3
Writes (WR) in DLL off mode
Table 23
General Timing Parameter
Parameter
Symbol
Limit Values
Unit
-16
-20
min
max
min
max
Write comm. to the first DQS latching
transition
Data-in and DM input pulse width
(each input)
(WL*tCK) - 0.5 (WL*tCK) +
(WL*tCK) - 0.5 (WL*tCK) +
tDQSS
tDIPW
ns
ns
0.5
—
0.5
—
0.77
0.88
DQS Write Preamble Time
DQS Write Postamble Time
Write to Read
0.55
0.88
8
—
0.63
1.0
8
—
1.5
—
—
tWPRE
tWPST
tWTR
tWR
ns
ns
ns
ns
1.32
—
Write to Precharge
14
—
14
ꢃꢇ
ꢂ
ꢃ
ꢄ
ꢅ
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ꢇ
ꢈ
ꢉ
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ꢌ
ꢃꢄ
ꢃꢅ
ꢃꢆ
#,+ꢀ
#,+
#OMꢁ
!DDRꢁ
72
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72
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7,ꢎ
7RITE ,ATENCY
Figure 61 DLL off: Write followed by Read
Data Sheet
75
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
