HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.4
Mode Register Set Command (MRS)
The mode register stores the data for controlling the
operating modes of the memory. It programs CAS
latency, test mode, DLL Reset and the value of the
write latency. There is no default value for the mode
register; therefore it must be written after power up to
operate the . During a Mode Register Set command
the address inputs are sampled and stored in the mode
register.
CLK#
CLK
CKE
CS#
tMRD must be met before any command can be issued
to the Graphics SDRAM. The Mode Register contents
can only be set or changed when the Graphics SDRAM
is in idle state.
RAS#
CAS#
WE#
A0-A11
BA0
COD
0
COD: Code to be loaded into
the register
BA1, BA2
0
Don't Care
Figure 19 Mode Register Set Command
A7
A6
A5
A4
A3
BT
A2
A1
BL
A0
BA2
BA1
BA0
A11
A10
WL
A9
A8
0
0
DLL
TM
CAS Latency
0
Burst Length
A1
A0
BL
A2
Write Latency
Testmode
mode
A11 A10
A9
WL
0
0
1
1
0
1
4
8
A7
0
1
1
0
1
0
3
4
0
1
Normal
RFU
all others
Testmode
all others
RFU
CAS Latency
Burst Type
BT
A6
A5
A4
Latency
DLL Reset
A3
A8
DLL Reset
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
8
9
0
1
sequential
RFU
0
1
No
10
11
7
Yes
all others
RFU
Note: 1) The DLL Reset command is self-clearing
Figure 20 Mode Register Bitmap
Data Sheet
40
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
