HYB18H512321AF
512-Mbit GDDR3
Functional Description
CLK#
CLK
Com.
PA
NOP
MRS
NOP
NOP
A.C.
NOP
RD
tMRD
tRP
tMRDR
MRS: MRS command
PA: PREALL command
A.C.: Any other command as READ
RD: READ command
Don't Care
Figure 21 Mode Register Set Timing
4.4.1
Burst length
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length of 4 and 8. This value
must be programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number
of column locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block if a boundary is reached. The starting location within this
block is determined by the two least significant bits A0 and A1 which are set internally to the fixed value of zero
each.
Reserved states should not be used, as unknow operation or incompatibility with future versions may result.
4.4.2
Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set
command (A3) . This device does not support the burst interleave mode.
Table 19
Burst Definition
Burst Length
Starting Column Adress
Order of Accesses within a Burst
(Type = sequential)
A2
—
0
A1
X
X
A0
X
X
4
8
0-1-2-3
0-1-2-3-4-5-6-7
4-5-6-7-0-1-2-3
1
X
X
The value applied at the balls A0 and A1 for the column address is “Don’t care”
4.4.3
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the
first bit of output data as shown on Figure 38
.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally
coincident with clock edge n+m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Data Sheet
41
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
