HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.4.4
Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability
of the first bit of input data as shown in Figure 28
.
4.4.5
Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits
A0-A6 and A8-A11 set to the desired value.
4.4.6
DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits
A0-A7 and A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command
with bit A8 set to one and bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns
automatically in the normal mode of operations once the DLL reset is completed.
Data Sheet
42
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
