HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.2.3
Dynamic Switching of DQ terminations
The GDDR3 Graphics RAM will disable its data terminators when a READ or DTERDIS command is detected. The
terminators are disabled starting at CL - 1 Clocks after the READ / DTERDIS command is detected and the
duration is 4 clocks. In a two rank system, both devices will snoop the bus for a READ / DTERDIS command to
either device and both will disable their terminators if a READ / DTERDIS command is detected. The address and
command terminators are always enabled.
0
1
2
5
6
7
8
9
10
11
CLK#
CLK
Com
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
.
Addr.
B / C
CAS latency = 7
RDQS
DQ
D0
D1
D2
D3
DQ
Termination
Data Terminations are disabled
Dx:
Data from B / C
B / C: Bank / Column address
RD: READ
N/D: NOP or Deselect
Com.: Command
Addr.: Address B / C
Don't Care
Figure 14 ODT Disable Timing during a READ command
4.2.4
Output impedance and Termination DC Electrical Characteristics
The Driver and Termination impedances are determined by applying VDDQ/2 nominal at the corresponding input /
output and by measuring the current flowing into or out of the device. VDDQ is set to the nominal value.
I
OH is the current flowing out of DQ when the Pull-Up transistor is activated and the DQ termination disabled.
IOLis the current flowing into DQ when the Pull-Down transistor is activated and the DQ termination disabled.
TCAH(ZQ) is the current flowing out of the Termination of Commands and Addresses for a ZQ termination value.
I
Table 17
DC Electrical Characteristics
Parameter
Nom.
240
Unit
Ω
Notes
ZQ Value
min
20.5
20.5
3.4
max
25.0
25.0
4.2
1)
1)
1)
IOH
IOL
ITCAH(ZQ)
ZQ/6
ZQ/6
ZQ
mA
mA
mA
1) Measurement performed with VDDQ (nominal) and by applying VDDQ/2 at the corresponding Input / Output.
0 °C ≤ Tc ≤ 85
Data Sheet
36
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
