HYB18H512321AF
512-Mbit GDDR3
Functional Description
CLK#
CLK
Command
PA
NOP
EMRS
NOP
NOP
A.C.
tRP
tMRD
A.C.: Any command
Don't Care
EMRS: Extended MRS command
PA: PREALL command
Figure 17 Extended Mode Register Set Timing
4.3.1
DLL enable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon
returning to normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is
enabled automatically). Anytime the DLL is enabled, 1000 cycles must occur before a READ command can be
issued.
4.3.2
WR
The WR parameter is programmed using the register bits A4, A5 and A7. This integer parameter defines as a
number of clock cycles the Write Recovery time in a Write with Autoprecharge operation.
The following inequality has to be complied with : WR * tCK ≥ tWR, where tCK is the clock cycle time.
4.3.3
Termination Rtt
The data termination, Rtt, is used to set the value of the internal termination resistors. The GDDR3 DRAM supports
ZQ / 4 and ZQ / 2 termination values. The termination may also be disabled for testing and other purposes.
4.3.4
Output Driver Impedance
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance.
When the autocalibration is used, the output driver impedance is set nominally to ZQ / 6.
4.3.5
Low Power
When the Low Power extended mode register is set, the device changes its internal self-refresh rate from 32 ms
to 8 ms. This allows self-refresh operation at higher temperatures for mobile applications.
Data Sheet
38
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
