HYB18H512321AF
512-Mbit GDDR3
Boundary Scan
Table 9
BIT#
1
2
3
4
5
6
7
8
9
10
11
12
Boundary Scan Exit) Order
BALL BIT# BALL BIT#
BALL BIT#
BALL BIT#
BALL BIT#
BALL
G-4
F-4
D-3
13
14
15
16
17
18
19
20
21
22
23
24
E-10
F-10
E-11
G-10
F-11
G-9
25
26
27
28
29
30
31
32
33
34
35
36
K-11
K-10
K-9
37
38
39
40
41
42
43
44
45
46
47
48
R-10
T-11
T-10
T-3
49
50
51
52
53
54
55
56
57
58
59
60
L-3
M-2
M-4
K-4
K-3
K-2
L-4
J-3
61
62
63
64
65
66
67
C-2
C-3
B-2
B-3
F-2
M-9
G-3
E-2
F-3
M-11
L-10
N-11
M-10
N-10
P-11
P-10
R-11
T-2
A-4
R-3
R-2
P-3
P-2
N-3
M-3
N-2
B-10
B-11
C-10
C-11
D-10
D-11
H-9
E-3
H-10
H-11
J-11
J-10
L-9
J-2
H-2
H-3
H-4
Notes
1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped.
2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after
scanning a bit #67, if the chip stays in scan shift mode.
3. Two RFU balls (#56 and #57) in the scan order, will read as a logic“0”.
Data Sheet
24
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
