HYB18H512321AF
512-Mbit GDDR3
Boundary Scan
Table 12
Scan AC Electrical Characteristics
PARAMETER/CONDITION
Scan Shift Time
SYMBOL
MIN
MAX UNITS NOTES
Scan clock to valid scan output
Scan clock to scan output hold
tSAC
tSOH
—
1.5
—
—
ns
ns
1
1
Notes
1. The parameter applies only when SEN is asserted.
2. Scan Enable should be issued earlier than other Scan Commands by 6 ns.
3.3
Scan Initilization
The initilization sequence for the boundary scan functionality depends on the intended SGRAM operation mode.
There are two modes to distinguish. The first mode is the Stand-Alone mode. In the Stand-Alone mode the
SGRAM is supposed to support the Boundary Scan functionality only, the user does not intend to operate the
DRAM in its ordinary functionality after or prior to the entering of the Boundary Scan functionality. The purpose of
the Stand-Alone mode could be a connectivity test at the manufacturing site.
The second mode is the regular SGRAM functionality. With this common mode the boundary scan functionality
can be enabled after the SGRAM has been initialized by the regular power-up and SGRAM initilization sequence.
When the boundary scan functionality is left the regular SGRAM initialization sequence has to be re-iterated.
3.3.1
Scan initilization for Stand-Alone Mode
The SGRAM needs to follow the given sequence to support the boundary scan functionality in the Stand-Alone
mode. There is no external clock for the whole sequence needed.
Sequence Flow:
1.) external Voltages (VDD/VDDQ/VREF) need to be stable for 200us, SEN has to be kept low
2.) bring SEN up to high state to enter boundary scan functionality
3.) operate boundary scan functionality according to the scan features given in Chapter 3.2
4.) boundary scan can be exited by bringing SEN low or simply by switching power off
The Scan initialization sequence for the Stand-Alone Mode is shown in Figure 7.
Data Sheet
27
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
