HYB18H512321AF
512-Mbit GDDR3
Boundary Scan
SCK
tSES
SEN
SSH
Low
tSCS
tSDS
tSDH
SON
Pins
under
Test
VALID
Don't Care
Figure 5
Scan Capture Timing
SCK
SEN
tSES
tSCS
SSH
SON
tSCS
SON
Scan Out
bit 0
Scan Out
bit 1
Scan Out
bit 2
Scan Out
bit 3
tSAC
tSOH
Don't Care
Figure 6
Table 12
Scan Shift Timing
Scan AC Electrical Characteristics
PARAMETER/CONDITION
Clock
SYMBOL
MIN
MAX UNITS NOTES
Clock cycle time
tSCK
40
—
ns
1
Scan Command Time
Scan enable setup time
Scan enable hold time
Scan command setup time for SSH, SOE and SOUT
Scan command hold time for SSH, SOE and SOUT
Scan Capture Time
tSES
tSEH
tSCS
tSCH
20
20
14
14
—
—
—
—
ns
ns
ns
ns
1)2
1
1
1
Scan capture setup time
Scan capture hold time
tSDS
tSDH
10
10
—
—
ns
ns
1
1
Data Sheet
26
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
