HYB18H512321AF
512-Mbit GDDR3
Pin Configuration
2.5.2
Function Truth Table for more than one Activated Bank
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel
due to the chip’s multibank architecture. The following table defines for which commands such a scheme is
possible. All other transitions are illegal. Notes 1-11 define the start and end of the actions belonging to a submitted
command. This table is based on the assumption that there are no other actions ongoing on bank n or bank m. If
there are any actions ongoing on a third bank tRRD, tRTW and tWTR have to be taken always into account.
Table 7
Function Truth Table I
Current State
ACTIVE
ongoing action on bank n
possible action in parallel on bank m
ACTIVATE 1)
ACT, PRE, WRITE, WRITE/A, READ, READ/A 2)
WRITE 3)
ACT, PRE, WRITE, WRITE/A, READ, READ/A4)
WRITE/A 5)
ACT, PRE, WRITE, WRITE/A, READ 6)
READ 7)
ACT, PRE, WRITE, WRITE/A, READ, READ/A8)
READ/A 9)
ACT, PRE, WRITE, WRITE/A, READ, READ/A 8)
PRECHARGE 10)
ACT, PRE, WRITE, WRITE/A, READ, READ/A 11)
PRECHARGE ALL 10)
POWER DOWN ENTRY 12)
ACTIVATE 1)
-
-
IDLE
ACT
POWER DOWN ENTRY 12)
AUTO REFRESH 13)
SELF REFRESH ENTRY 12)
MODE REGISTER SET (MRS)14)
EXTENDED MRS 14)
POWER DOWN EXIT 15)
SELF REFRESH EXIT 16)
-
-
-
-
-
-
-
POWER DOWN
SELF REFRESH
1) Action ACTIVATE starts with issuing the command and ends after tRCD
.
2) During action ACTIVATE an ACT command on another bank is allowed considering tRRD, a PRE command on another bank
is allowed any time. WR, WR/A, RD and RD/A are always allowed.
3) Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling
WDQS edge.
4) during action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on
another bank must be separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before tWTR
is met.
5) Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling
WDQS edge.
6) during action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command
on another bank has to be separated by at least one NOP from the ongoing command. RD is not allowed before tWTR is
met. RD/A is not allowed during an ongoing WRITE/A action.
7) Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge
of RDQS.
8) during action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A
command on another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command
on another bank has to meet tRTW
.
9) Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge
of RDQS.
10) Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after tRP
.
11) During Action ACTIVE an ACT command on another banks is allowed considering tRRD. A PRE command on another bank
is allowed any time. WR, WR/A, RD and RD/A are always allowed.
12) During POWER DOWN and SELF REFRESH only the EXIT commands are allowed.
Data Sheet
21
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
