HYB18H512321AF
512-Mbit GDDR3
Boundary Scan
3
Boundary Scan
3.1
General Description
The 512Mb GDDR3 incorporates a modified boundary scan test mode. This mode doesn’t operate in accordance
with IEEE Standard 1149.1-1990. To save the current GDDR3 ball-out, this mode will scan the parallel data input
and output the scanned data through the WDQS0 pin controlled by SEN.
3.2
Disabling the scan feature
It is possible to operate the 512Mb GDDR3 without using the boundary scan feature. SEN (at U-4 of 136- ball
package) should be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins
which are used for scan mode, RES, MF, WDQS0 and CS will be operating at normal GDDR3 functionalities when
SEN is deasserted.
Dedicated Scan Flops
(1 per signal under test)
Tie to logic 0
D
DM0
DQ
CK
Pins under test
D
DQ5
DQ
CK
D
DQ4
DQ
CK
The following lists the rest of the signals on the scan chain:
DQ[3:0], DQ[31:6], RDQS[3:1], WDQS[3:1], DM[3:1],
CAS, WE, CKE, BA[2:0], A[11:0], CK, CK and ZQ
Two RFU’s (J-2 and J-3 on 136-ball package) will be on
the scan chain and will read as a logic "0"
D
RDQS0
DQ
The following lists the signals not on the scan chain:
VDD, VSS, VDDQ, VSSQ, VDDA, VSSA and VREF
CK
RES (SSH, Scan Shift)
CS (SCK, Scan Clock)
WDQS0 (SOUT, Scan Out)
SEN, Scan Enable
Puts device into scan mode and re-maps pins to scan functionality
MF (SOE, Output Enable)
Figure 4
Data Sheet
Internal Block Diagram (Reference only)
23
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
