September 2006
rev 0.2
PCS2P5T915A
Differential Input AC Test Conditions for HSTL
Symbol
VDIF
VX
VTHI
tR, tF
Parameter
Value
1
750
Units
V
mV
V
Input Signal Swing1
Differential Input Signal Crossing Point2
Input Timing Measurement Reference Level3
Input Signal Edge Rate4
Crossing Point
1
V/nS
Notes: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
Compliant devices must meet the VDIF (AC) specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices
must meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics Over Operating Range for eHSTL1
Symbol
Parameter
Test Conditions
Min
Typ7
Max
Unit
Input Characteristics
IIH
IIL
VIK
VIN
VDIF
Input HIGH Current9
VDD= 2.6V
VDD= 2.6V
VDD= 2.4V, IIN = -18mA
VI = VDDQ/GND
VI = GND/VDDQ
±5
±5
- 1.2
+3.6
µA
Input LOW Current9
Clamp Diode Voltage
DC Input Voltage
- 0.7
900
V
V
V
-0.3
0.2
DC Differential Voltage2,8
DC Common Mode Input
VCM
800
1000
mV
Voltage3,8
VIH
VIL
DC Input HIGH4,5,8
DC Input LOW4,6,8
VREF+ 100
mV
mV
VREF- 100
Single-Ended Reference
VREF
900
mV
Voltage4,8
Output Characteristics
IOH= -8mA
VDDQ- 0.4
VDDQ- 0.1
V
V
V
V
VOH
Output HIGH Voltage
IOH= -100µA
IOL= 8mA
IOL= 100µA
0.4
0.1
VOL
Output LOW Voltage
Notes: 1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement"
input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input
interface table should be referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
7 of 23
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
