September 2006
rev 0.2
PCS2P5T915A
Pin Configuration
48
VDDQ
GND
VDD
VDD
5
VDDQ
8
Q2
Q1
40
39
VDDQ
PCS2P5T915A
VDDQ
Q3
VDDQ
VDDQ
35
34
16
VDDQ
Q4
VDDQ
22
G(-)
VDD
VDDQ
GND
VDDQ
VDD
GND
24
25
Absolute Maximum Ratings1
Notes: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met.
3. Not to exceed 3.6V.
Symbol
VDD
VDDQ
VI
VO
VREF
TSTG
Description
Power Supply Voltage2
Output Power Supply2
Input Voltage
Max
Unit
V
V
V
V
-0.5 to +3.6
-0.5 to +3.6
-0.5 to +3.6
-0.5 to VDDQ +0.5
-0.5 to +3.6
-65 to +165
Output Voltage3
Reference Voltage3
Storage Temperature
V
° C
TJ
Junction Temperature
150
° C
Capacitance1,2 (TA = +25°C, F = 1.0MHz)
Symbol
Parameter
Min
Typ
Max
Unit
pF
CIN
Input Capacitance
3.5
Notes: 1. This parameter is measured at characterization but not tested.
2. Capacitance applies to all inputs except RxS and TxS.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
3 of 23
Notice: The information in this document is subject to change without notice.