September 2006
PCS2P5T915A
rev 0.2
DC Electrical Characteristics Over Operating Range for 1.8V LVTTL1
Symbol
Parameter
Test Conditions
Min
Typ8
Max
Unit
Input Characteristics
IIH
IIL
VIK
VIN
Input HIGH Current12
Input LOW Current12
Clamp Diode Voltage
DC Input Voltage
VDD= 2.6V
VDD= 2.6V
VDD= 2.4V, IIN= -18mA
VI = VDDQ/GND
VI = GND/VDDQ
±5
±5
- 1.2
µA
-0.7
V
V
- 0.3
VDDQ+ 0.3
Single-Ended Inputs2
VIH
DC Input HIGH
1.07311
V
V
VIL
DC Input LOW
0.68311
Differential Inputs
VDIF
DC Differential Voltage3,9
0.2
825
V
DC Common Mode Input
VCM
900
900
975
mV
Voltage4,9
VIH
VIL
DC Input HIGH5,6,9
DC Input LOW5,7,9
VREF+ 100
mV
mV
VREF- 100
Single-Ended Reference
VREF
mV
Voltage5,9
Output Characteristics
IOH= -6mA
IOH= -100µA
IOL= 6mA
VDDQ- 0.4
VDDQ- 0.1
V
V
V
V
VOH
Output HIGH Voltage
0.4
0.1
VOL
Output LOW Voltage
IOL= 100µA
Notes: 1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement"
input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when
VREF is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee
switching in voltage range specified in the JEDEC 1.8V LVTTL interface specification, VREF must be maintained at 900mV with appropriate
tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The
correct input interface table should be referenced.
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 • VDD
where VDD is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the
specification, the translator was designed to accept the calculated worst case value ( VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a
nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 • VDD
where VDD is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure
compliance with the specification, the translator was designed to accept the calculated worst case value ( VIL = 0.35 • [1.8 + 0.15V])
rather than reference against a nominal 1.8V supply.
12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
11 of 23
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
