September 2006
PCS2P5T915A
rev 0.2
DC Electrical Characteristics Over Operating Range for HSTL1
Symbol
Parameter
Test Conditions
Min
Typ7
Max
Unit
Input Characteristics
IIH
IIL
VIK
VIN
VDIF
Input HIGH Current9
VDD= 2.6V
VDD= 2.6V
VI = VDDQ/GND
VI = GND/VDDQ
±5
±5
- 1.2
+3.6
µA
Input LOW Current9
Clamp Diode Voltage
DC Input Voltage
VDD= 2.4V, IIN= - 18mA
-0.7
V
V
V
-0.3
0.2
DC Differential Voltage2,8
DC Common Mode Input
VCM
680
750
750
900
mV
Voltage3,8
VIH
VIL
VREF
DC Input HIGH4,5,8
DC Input LOW4,6,8
VREF+ 100
mV
mV
mV
VREF- 100
Single-Ended Reference
Voltage4,8
Output Characteristics
IOH= -8mA
IOH= -100µA
V
DDQ- 0.4
V
V
V
VOH
Output HIGH Voltage
VDDQ- 0.1
IOL= 8mA
IOL= 100µA
0.4
0.1
VOL
Output LOW Voltage
V
Notes: 1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement"
input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF
.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input
interface table should be referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Power Supply Characteristics for HSTL Outputs1
Symbol
Parameter
Test Conditions2
Typ Max Unit
Quiescent VDD Power
Supply Current
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
VDDQ= Max., Reference Clock = LOW3
IDDQ
20
30
mA
Quiescent VDDQ Power
Supply Current
IDDQQ
0.1
0.3
mA
Outputs enabled, All outputs unloaded
Dynamic VDD Power
Supply Current per
Output
Dynamic VDDQ Power
Supply Current per
Output
IDDD
V
DD= Max., VDDQ= Max., CL= 0pF
DD= Max., VDDQ= Max., CL= 0pF
20
30
µA/MHz
µA/MHz
IDDDQ
V
30
50
Total Power VDD Supply
VDDQ= 1.5V, FREFERENCE CLOCK= 100MHz,CL= 15pF
DDQ= 1.5V, FREFERENCE CLOCK= 250MHz, CL= 15pF
VDDQ= 1.5V, FREFERENCE CLOCK= 100MHz, CL= 15pF
VDDQ= 1.5V, FREFERENCE CLOCK= 250MHz, CL= 15pF
20
35
35
60
40
50
70
ITOT
mA
mA
Current
V
Total Power VDDQ Supply
Current
ITOTQ
120
Note: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
6 of 23
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
