November 2006
rev 1.5
ASM5P2308A
Switching Characteristics for ASM5P2308A Commercial Temperature Devices
Description
Test Conditions
Min
15
Typ
Max
100
133
133
Unit
MHz
MHz
MHz
Parameter
1/t1
1/t1
t1/
Output Frequency
30pF load, All devices
20pF load, -1H, -5H devices 8
Output Frequency
15
Output Frequency
15pF load, -1, -2, -3, -4 devices
15
Duty Cycle 9= (t2 / t1) * 100
(-1, -2, -3, -4, -1H, -5H)
Duty Cycle 9= (t2 / t1) * 100
(-1, -2, -3, -4, -1H, -5H)
Output Rise Time 9
(-1, -2, -3, -4)
Measured at 1.4V, FOUT = <66.66MHz
30pF load
40.0
45.0
50.0
50.0
60.0
55.0
2.20
1.50
1.50
2.20
1.50
1.25
200
%
Measured at 1.4V, FOUT = <50MHz
15pF load
%
t3
t3
t3
t4
t4
t4
Measured between 0.8V and 2.0V 30pF load
Measured between 0.8V and 2.0V 15pF load
Measured between 0.8V and 2.0V 30pF load
Measured between 2.0V and 0.8V 30pF load
Measured between 0.8V and 2.0V 15pF load
Measured between 2.0V and 0.8V 30pF load
All outputs equally loaded
nS
nS
nS
nS
nS
nS
pS
Output Rise Time 9
(-1, -2, -3, -4)
Output Rise Time 9
(-1H, -5H)
Output Fall Time 9
(-1, -2, -3, -4)
Output Fall Time 9
(-1, -2, -3, -4)
Output Fall Time 9
(-1H, -5H)
Output-to-output skew on same
bank (-1, -2, -3, -4) 9
Output-to-output skew
(-1H, -5H)
All outputs equally loaded
200
t5
Output bank A -to- output
Bank B skew (-1, -4, -5H)
Output bank A -to- output
Bank B skew (-2, -3)
Delay, REF Rising Edge to FBK
Rising Edge 9
All outputs equally loaded
200
All outputs equally loaded
400
t6
t7
Measured at VDD /2
0
0
±250
pS
Device-to-Device Skew 9
Measured at VDD/2 on the FBK pins of the device
Measured at 66.67MHz, loaded outputs, 15pF load
Measured at 66.67MHz, loaded outputs, 30pF load
700
200
200
pS
pS
Cycle-to-cycle jitter 9
(-1, -1H, -4, -5H)
tJ
Measured at 133.3MHz, loaded outputs, 15pF
load
100
400
400
Measured at 66.67MHz, loaded outputs, 30pF load
pS
Cycle-to-cycle jitter 9
(-2, -3)
tJ
Measured at 66.67MHz, loaded outputs, 15pF
load
tLOCK
Stable power supply, valid clock presented on REF
and FBK pins
PLL Lock Time 9
1.0
mS
Note:
9. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
16 of 16
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
