November 2006
rev 1.5
ASM5P2308A
Block Diagram
FBK
/2
PLL
MUX
REF
/2
CLKA1
CLKA2
CLKA3
CLKA4
Extra Divider (-5H)
Extra Divider (-3, -4)
S2
S1
Select Input
Decoding
/2
CLKB1
CLKB2
CLKB3
CLKB4
Extra Divider (-2, -3)
Select Input Decoding for ASM5P2308A
S2
0
S1
0
Clock A1 - A4
Three-state
Driven
Clock B1 - B4
Three-state
Three-state
Driven
Output Source
PLL Shut-Down
PLL
Y
N
Y
N
0
1
PLL
1
0
Driven1
Reference
PLL
1
1
Driven
Driven
ASM5P2308A Configurations
Device
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank A Frequency
Bank B Frequency
Reference
ASM5P2308A-1
ASM5P2308A-1H
ASM5P2308A-2
ASM5P2308A-2
ASM5P2308A-3
ASM5P2308A-3
ASM5P2308A-4
ASM5P2308A-5H
Note:
Reference
Reference
Reference
Reference
Reference /2
Bank B
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference /2
Reference
Bank A
Reference or Reference2
2 X Reference
2 X Reference
Reference /2
Bank B
Bank A or Bank B
Bank A or Bank B
1. Outputs are non- inverted on 2308A-2 and 2308A-3 in bypass mode, S2 = 1 and S1 = 0.
2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P2308A-2.
3.3V Zero Delay Buffer
2 of 17
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
