November 2006
rev 1.5
ASM5P2308A
Pin Configuration
REF
CLKA1
1
2
16
15
FBK
CLKA4
CLKA3
CLKA2
VDD
3
4
5
6
14
13
12
11
ASM5P2308A
VDD
GND
CLKB4
GND
CLKB1
10 CLKB3
CLKB2
S2
7
8
9
S1
Pin Description for ASM5P2308A
Pin #
1
2
3
4
Pin Name
REF3
Description
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
CLKA14
CLKA24
VDD
5
6
7
8
GND
Ground
CLKB14
CLKB2 4
S2 5
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
9
S1 5
Select input, bit 1
10
11
12
13
14
15
16
CLKB3 4
CLKB4 4
GND
Buffered clock output, bank B
Buffered clock output, bank B
Ground
VDD
3.3V supply
CLKA3 4
CLKA4 4
FBK
Buffered clock output, bank A
Buffered clock output, bank A
PLL feedback input
Notes:
3. Weak pull-down.
4. Weak pull-down on all outputs.
5. Weak pull-up on these inputs.
3.3V Zero Delay Buffer
16 of 16
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
