8.3
Signal Specifications
Parameter
Conditions/Description
SYNC/DATA Line
Min
Nom
Max
Units
SDpu
SD pull up resistor
SD input low voltage threshold
SD input high voltage threshold
SD input hysteresis
5
kΩ
V
SDthrL
0.31·VDD
0.45·VDD
0.37
0.52·VDD
0.81·VDD
1.1
SDthrH
SDhys
V
V
SDsink
Freq_sd
SD sink capability (VSD=0.5V)
Clock frequency
30
mA
kHz
450
22
550
% of clock
cycle
% of clock
cycle
Tsynq
T0
Sync pulse duration
28
78
Data=0 pulse duration
72
Interrupt Inputs (INT_N[3:0])
Pull up resistor
Rpu3
VthrL3
VthrH3
Vhys3
30
kΩ
V
Input low voltage threshold
Input high voltage threshold
Input hysteresis
0.31·VDD
0.45·VDD
0.37
0.52·VDD
0.81·VDD
1.1
V
V
ADDR[3:0], ACFAIL_N, RES_N, LCK_N, PG[3:0] Inputs
Rpu1
VthrL1
VthrH1
Pull up resistor
Input low voltage
Input high voltage
20
-0.5
50
kΩ
V
0.2·VDD
VDD+0.5
0.7·VDD
V
HRES_N Input
HRES_N pull up resistor (with series
diode, see note 1)
Rpu2
30
60
kΩ
VthrL2
VthrH2
HRES_N input low voltage
HRES_N input high voltage
-0.5
0.2·VDD
VDD+0.5
V
V
0.9·VDD
Inputs/Outputs (OK_A, OK_B, OK_C, OK_D)
OKpu
OKthrL
OKthrH
OKhys
OKsink
OK pull up resistor
5
kΩ
V
OK input low voltage threshold
OK input high voltage threshold
OK input hysteresis
0.31·VDD
0.45·VDD
0.37
0.52·VDD
0.81·VDD
1.1
V
V
OK sink capability (VOK=0.5V)
30
mA
Enable Outputs (EN[3:0])
VEN
VEN
EN logic level enabled
EN logic level disabled
High
Low
EN output high voltage
IOH = -10 mA
EN output low voltage
IOL = 5 mA
VEN
H
VDD-0.6
V
V
VEN
L
0.5
______________________________________
1
HRES_N Input - Because the input does not have an internal ESD protection diode connected to VDD, the user needs to add an external diode between the
HRES_N and VDD pins as shown in Figure 3.
ZD-00896 Rev. 5.2, 9-Apr-13
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