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DM7304G 参数 Datasheet PDF下载

DM7304G图片预览
型号: DM7304G
PDF下载: 下载PDF文件 查看货源
内容描述: DM7300G系列数字电源管理器 [DM7300G Series Digital Power Manager]
分类和应用:
文件页数/大小: 36 页 / 1964 K
品牌: POWER-ONE [ POWER-ONE ]
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8.4  
I2C Interface  
Parameter  
Conditions/Description  
Input low voltage  
Min  
-0.5  
Nom  
Max  
Units  
V
ViL  
ViH  
Vhys  
VoL  
tr  
0.3·VDD  
VDD+0.5  
Input high voltage  
0.7·VDD  
0.05·VDD  
0
V
Input hysteresis  
V
Output low voltage, ISINK=3mA  
Rise time for SDA and SCL  
Output fall time from ViHmin to ViLmax  
Input current each I/O pin, 0.1VDD<Vi<0.9VDD  
Capacitance for each I/O pin  
SCL clock frequency  
0.4  
300  
250  
10  
V
1
20+0.1Cb  
ns  
ns  
µA  
pF  
kHz  
1
tof  
20+0.1Cb  
Ii  
-10  
Ci  
10  
fSCL  
0
400  
Standard-Mode I2C (fSCL 100kHz)  
1
RPU  
tHDSTA  
tLOW  
External pull-up resistor  
Hold time (repeated) START condition  
Low period of the SCL clock  
1
1000/Cb  
kΩ  
µs  
µs  
µs  
µs  
µs  
ns  
µs  
µs  
4.0  
4.7  
4.0  
4.7  
0
tHIGH  
High period of the SCL clock  
tSUSTA  
tHDDAT  
tSUDAT  
tSUSTD  
tSUF  
Setup time for a repeated START condition  
Data hold time  
3.45  
Data setup time  
250  
4.0  
4.7  
Setup time for STOP condition  
Bus free time between a STOP and START condition  
Fast-Mode I2C (100kHz < fSCL≤ 400kHz)  
1
RPU  
tHDSTA  
tLOW  
External pull-up resistor  
Hold time (repeated) START condition  
Low period of the SCL clock  
1
300/Cb  
kΩ  
µs  
µs  
µs  
µs  
µs  
ns  
µs  
µs  
0.6  
1.3  
0.6  
0.6  
0
tHIGH  
High period of the SCL clock  
tSUSTA  
tHDDAT  
tSUDAT  
tSUSTD  
tSUF  
Setup time for a repeated START condition  
Data hold time  
0.9  
Data setup time  
100  
0.6  
1.3  
Setup time for STOP condition  
Bus free time between a STOP and START condition  
______________________________________  
1
Cb – bus capacitance in pF, typically from 10pF to 400pF  
ZD-00896 Rev. 5.2, 9-Apr-13  
www.power-one.com Page 7 of 36  
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