RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
4.4.2.5 General Interrupt Register
Symbol: XIR
Address Offset: 00010h
Default Value: 00000000h
Access:
Read only
Interrupt Register.
Bits
Description
31:3
Reserved.
Ready Active. This is the logical OR of the Ready Active Interrupt register, after it has been
masked. This is set if a serial link goes from inactive to active and the corresponding mask bit is
1. This bit is not cleared when read. You must clear the Ready Active Interrupt register.
2
Ready Inactive. This is the logical OR of the Ready Inactive Interrupt register, after it has been
masked. This is set if a serial link goes from active to inactive and the corresponding mask bit is
1. This bit is not cleared when read. You must clear the Ready Inactive Interrupt register.
1
0
CRC Error. This is the logical OR of the CRC register, after it has been masked. This is set if a
CRC error occurs and the corresponding mask bit is 1. This bit is not cleared when read. You
must clear the CRC Error Interrupts register.
4.4.2.6 CRC Error Interrupts Mask
Symbol: XCRCMSK
Address Offset: 00014h
Default Value: 00000000h
Access:
Read/Write
Interrupt Mask for per-port CRC errors
Bits
Description
CRC Error Interrupts Mask. Each bit is used to mask (enable) interrupts when the
corresponding bit in the CRC Error Interrupts register is set to 1. The interrupt is enabled when
the bit is 1.
31:0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
231
PMC [ PMC-SIERRA, INC ]
