RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
4.4 CROSSBAR REGISTERS
The Crossbar device select low-order bits are hard wired on the board by four pins (oobdev_sel[3:0]) on
the Crossbar package. See Section 1.7.1.3 “Individual Device Selects” on page 79 for more information.
4.4.1 Summary
The following table is a summary of information for all registers in the Crossbar. See the following
Descriptions section for more information on individual registers.
Read and Clear means that reading the register causes it to be cleared (reset to zero)
Table 37. Crossbar Register Summary
Default
Value
Address
Symbol
XSTS
Register
Access
00000h
00004h
00008h
0000Ch
00010h
00014h
Status
Read Only
Read/Write
Read/Write
Read/Write
Read only
Read/Write
40000000h
00000004h
00000000h
00000000h
00000000h
00000000h
XMODERS
XIRLMSK
XIRHMSK
XIR
Control/Reset
Low Priority Mask
High Priority Mask
General Interrupt Register
CRC Error Interrupts Mask
XCRCMSK
Read and
Clear
00018h
0001Ch
00020h
00024h
00028h
XCRC
CRC Error Interrupts
00000000h
00000000h
00000000h
00000000h
00000000h
XRDYDMSK RDY Inactive Interrupts Mask
XRDYDN Link RDY Inactive Interrupts
XRDYUMSK Link RDY Active Interrupts Mask
Read/Write
Read and
Clear
Read/Write
Read and
Clear
XRDYUP
Link RDY Active Interrupts
00030h
00034h
0003Ch
00100h
XAIBRS
XAIBRDY
XAIBEN
XPLL
AIB Reset
Read/Write
Read Only
Read/Write
Read/Write
FFFFFFFFh
00000000h
00000000h
0001447Ch
AIB Ready
AIB Tx Enable
PLL Control/Status
228
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
