PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
3.4.2.53 End of Sch Refresh/Sch OC-48 Sync ModCount
Symbol: EESR48SD
Address Offset: 000D4h
Default Value: 00000000h
Access:
Write Only
Specifies the value of an internal OC-48 Sync counter at which the OOB Go Schedulers command should
trigger the end of Scheduler refresh.
Bits
Description
31:5
Reserved.
Prevents OC-48 Sync phase change after Scheduler refresh. The value of this register
will not require adjustment unless there is a change in timing in a future revision of the EPP or
Scheduler.
4:0
3.4.2.54 PLL Status/Control
Symbol: EPLLREG
Address Offset: 00100h
Default Value: 0001447Ch
Access:
Read/Write
For more details, refer to the IBM SA-12E databook.
Bits
Description
31:21 Reserved.
30:20 PLL_OBSERVE (read only).
19:17 Reserved
PLL_RESET. When set, VCO is held at minimum frequency and PLL is bypassed. PLL reset
takes 10mS to complete.
16
15:10 PLL_TUNE.
9:6
5:3
2:0
PLL_MULT.
PLL_RANGE_B.
PLL_RANGE_A.
196
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
