PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Data
Bits
Description
31:20 Reserved.
19:10 Linecard TDM Tag Head
9:0 Request Count
For Control Packet: Each request count is 3 bits wide. Each request count corresponds to a 7-deep,
1-bit-wide FIFO. Whenever OOB changes a request count value, it should also supply any tags
associated with requests in the upper data bits. The LSB of the “Control Packet Tag FIFO” field is the head
of the tag FIFO, i.e. the next tag that will be sent with a grant.
Address
Bits
Description
19:15 Must be set to 0x1
14:13 Source Subport
12:9
8:4
3:2
1:0
Must be set to 0x0 for Control Packet Traffic type
Must be set to 0
Destination Subport
Must be set to 0
Data
Bits
31:10 Reserved.
Description
9:3
2:0
Control Packet Tag Head
Request Count
3.4.2.59 Input Queue Information Memory
Symbol: EIQIM
Address Offset: 16000-17FFCh
Default Value: 000000000h
Access:
Read/Write
This memory is addressed by QID. This memory contains input queue information for 4 TDM, 4 multicast,
128 unicast, and 4 control packet queues.
For Unicast Traffic: 128-512 queues depending on Egress OC48 Mode Map register; each OC-192
queue holds 0-64 cells, each OC-48 queue holds 0-16 cells.
200
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
