PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
3.4.2.49 Idle Count Value
Symbol:
EIDLCT
Address Offset: 000C4h
Default Value: 00000000h
Access:
Read/Write
This register is used to compensate for the clock frequency variation between the ETT1 switch and the linecard.
Bits
Description
Idle Count Value. This represents the frequency of sending idle frames to the line card. This
register is used to compensate for the clock frequency variation between the ETT1 switch and
the linecard. If this register is set to 0x0, only idle frames are transmitted to the linecard. If this
register is set to 0xFFFFFFFF, no idle frames are transmitted. If this register is set to N, an idle
frame is sent every N + 1 frame times. Note that this register resets to 0x0.
31:0
3.4.2.50 Enable TDM Sync Generation
Symbol: ETDMEN
Address Offset: 000C8h
Default Value: 00000000h
Access:
Read/Write
Indicates if the TDM sync generation is enabled (1) or disabled (0).
Bits
Description
31:1
Reserved.
Enable TDM Sync Generation. This bit indicates if the TDM sync generation is enabled (1)
or disabled (0). If the linecard chooses not to provide the TDM sync signal, any one of the EPPs
can be programmed to generate this signal.
0
194
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
