PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
3.4.2.46 Fault Tolerance Status/Control
Symbol: EFTCTRL
Address Offset: 000B8h
Default Value: 00000000h
Access:
Read/Write
Fault Tolerence Status/Control Register.
Bits
Description
31:5
Reserved
Primary Flow Control Crossbar B Select. This bit specifies which Flow Control Crossbar B
is primary. If this bit is 0, then Flow Control Crossbar B 0 is primary. If this bit is 1, then Flow
Control Crossbar B 1 is primary. This bit is both a status and control bit. When the primary
Flow Control Crossbar B goes down, the EPP must switch over to the secondary Flow Control
Crossbar B (causes this bit to flip). OOB can also change the configuration.
4
Primary Flow Control Crossbar A Select. This bit specifies which Flow Control Crossbar A
is primary. If this bit is 0, then Flow Control Crossbar A 0 is primary. If this bit is 1, then Flow
Control Crossbar A 1 is primary. This bit is both a status and control bit. When the primary
Flow Control Crossbar A goes down, the EPP must switch over to the secondary Flow Control
Crossbar A (causes this bit to flip). OOB can also change the configuration.
3
2
1
0
Ignore Central Scheduler Grants. This bit indicates that the EPP is ignoring grants from
both primary and secondary central schedulers. The EPP asserts this bit if both schedulers
have transmitted CRC errors in the same frame, if the only operational scheduler has
transmitted a CRC error, or if the only operational scheduler’s AIB link dropped ready. Note that
the OOB must write a 0 to this bit to clear it.
Freeze Scheduler Request Modulator (Multicast & Unicast only). This bit indicates that
the SRM is frozen (TDM traffic can still flow) due to fault tolerance errors. The EPP asserts this
bit if both schedulers have transmitted CRC errors in the same frame, if the only operational
scheduler has transmitted a CRC error, or if the only operational scheduler’s AIB link dropped
ready. Note that the OOB must write a 0 to this bit to clear it.
Primary Scheduler Select. This bit specifies which scheduler is primary. If this bit is 0, then
scheduler 0 is primary. If this bit is 1, then scheduler 1 is primary. This value must be consistent
on all the port processors. This bit is both a status and control bit. When the primary scheduler
goes down, all EPPs must switch over to the secondary scheduler (causes this bit to flip). The
OOB processor can also change the configuration.
192
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
