PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
3.4.2.39 Internal Delay Matching Adjustments
Symbol: EIDMA
Address Offset: 0009Ch
Default Value: 03A8D66Bh
Access:
Read/Write
Delay matching
Bits
Description
31:29 Reserved
DS iFIFO Token Mechanism Delay. Specifies the depth of the token shift register. Default at
reset is 0x0. See Appendix C.2.2.1 for details.
28:27
Flow Control Crossbar oEPP->iEPP Delay. Specifies the time it takes for a Flow Control
26:23 frame to reach the iEPP after it sent from any oEPP. The value of this register will not require
adjustment unless there is a change in timing in a future revision of the EPP or Crossbar.
Unicast Scheduler Request to Waiting Delay. Specifies the minimum delay for a priority 0
22:18 UC scheduler request to be granted. The value of this register will not require adjustment
unless there is a change in timing in a future revision of the EPP or Scheduler.
TDM Ingress Subport to Scheduler Grant Delay. Specifies the delay between a valid input
TDM slot and the corresponding scheduler TDM grant. The value of this register will not
require adjustment unless there is a change in timing in a future revision of the EPP or
17:12
Scheduler.
TDM Egress Fanout Delay. Specifies the delay between a valid output TDM slot and the
11:6
5:0
arrival of the TDM cell. The value of this register will not require adjustment unless there is a
change in timing in a future revision of the EPP, DS, Crossbar or Scheduler.
LCS Unicast Grant to Scheduler Request Delay. The value of this register will not require
adjustment, provided that the customer can meet the RTT constraint given in Section 1.1
“Preventing Underflow of the VOQ” on page 327.
188
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
