PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Bits
Description (Continued)
Received Multicast Cell with Invalid Fanout. This is set if a multicast cell arrives and its
tag’s fanout is all-0s.
19
CRC Error in LCS Header from LC??. This is set if an incoming cell has an LCS header
CRC error or has a code error in input dataslices 0, 1, or 2. Since the MUX field of the request
label could be corrupted, the source subport is unknown.
18
CRC Error in Processed Control Packet from Subport 3. This is set if there is a CRC
Error over the first 10 bytes of payload data for a PCP from Subport 3.
17
16
15
14
13
12
11
10
9
CRC Error in Processed Control Packet from Subport 2. This is set if there is a CRC
Error over the first 10 bytes of payload data for a PCP from Subport 2.
CRC Error in Processed Control Packet from Subport 1. This is set if there is a CRC
Error over the first 10 bytes of payload data for a PCP from Subport 1.
CRC Error in Processed Control Packet from Subport 0. This is set if there is a CRC
Error over the first 10 bytes of payload data for a PCP from Subport 0.
Received LCS Start Control Packet. This notifies OOB that a Subport has sent a
Processed Control Packet of type “LCS Start”.
Received LCS Stop Control Packet. This notifies OOB that a Subport has sent a
Processed Control Packet of type “LCS Stop”.
Received LC2OOB/CPU Control Packet from Subport 3. This notifies OOB that Subport
3 has sent a CPU Control Packet.
Received LC2OOB/CPU Control Packet from Subport 2. This notifies OOB that Subport
2 has sent a CPU Control Packet.
Received LC2OOB/CPU Control Packet from Subport 1. This notifies OOB that Subport
1 has sent a CPU Control Packet.
Received LC2OOB/CPU Control Packet from Subport 0. This notifies OOB that Subport
0 has sent a CPU Control Packet.
8
LC2OOB/CPU Control Packet FIFO Overflow, Subport 3. This is set if Subport 3
overflows its 8-cell FIFO of CPU Control Packets to OOB.
7
LC2OOB/CPU Control Packet FIFO Overflow, Subport 2. This is set if Subport 2
overflows its 8-cell FIFO of CPU Control Packets to OOB.
6
LC2OOB/CPU Control Packet FIFO Overflow, Subport 1. This is set if Subport 1
overflows its 8-cell FIFO of CPU Control Packets to OOB.
5
LC2OOB/CPU Control Packet FIFO Overflow, Subport 0. This is set if Subport 0
overflows its 8-cell FIFO of CPU Control Packets to OOB.
4
Line Card Request Count Overflow. This is set if a Subport sends too many requests (the
counter will stick at max value).
3
Scheduler Grant to Empty UC Queue. This is set if the scheduler grants to an empty UC
input queue (VOQ).
2
Output MC or UC Queue Overflow. This is set if a cell from the crossbar overflows a MC or
UC output queue.
1
0
Output TDM Queue Overflow. This is set if a cell from the Crossbar overflows a TDM output
queue.
172
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
