Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Bits
Description (Continued)
Scheduler Both Links CRC Error. If set, traffic for this port is frozen and OOB must initiate
Scheduler Refresh to repair Scheduler state for this port.
1
Scheduler Frame Mismatch. Though apparently valid, the frames received from Sched0
and Sched1 were not identical. In this case the Primary Sched is selected.
0
3.4.2.9 Low Priority Incremental Credit Interrupt Mask
Symbol: ELPICIR
Address Offset: 00020h
Default Value: 00000000h
Access:
Read/Write
Enables a low priority interrup
Bits
Description
Mask bits for low priority interrupts. Each mask bit is set to 1 to enable a low priority
interrupt when the corresponding bit in the Invalid Incremental Credit Interrupt register is 1.
31:0
3.4.2.10 High Priority Incremental Credit Interrupt Mask
Symbol: EHPICIR
Address Offset: 00024h
Default Value: 00000000h
Access:
Read/Write
Enables a high priority interrupt.
Bits
Description
Mask bits for High priority interrupts. Each mask bit is set to 1 to enable a high priority
interrupt when the corresponding bit in the Invalid Incremental Credit Interrupt register is 1.
31:0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
175
PMC [ PMC-SIERRA, INC ]
