Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
2.3 DATASLICE REGISTERS
The Dataslice device select low-order bits are hard wired on the board by three pins (oobdev_sel[2:0]) on
the Dataslice package. Since there are two logical Dataslices within each package, the fourth implied bit is
used to select which of the two logical Dataslices is addressed.
2.3.1 Dataslice Summary
The following table is a summary of information for all registers in the Dataslice. See the following
Descriptions section for more information on individual registers.
Read and Clear means that reading the register causes it to be cleared (reset to zero)
Table 21. Dataslice Register Summary
Default
Value
Address
00000h
Symbol
DSTS
Register
Access
Status
Reset
Read Only
Read/Write
Read/Write
Read/Write
10000000h
00000004h
00000000h
00000000h
00004h
00008h
0000Ch
DRS
DIRLMSK
DIRHMSK
Low Priority Mask
High Priority Mask
Read and
Clear
00010h
DIR
Interrupt Register
00000000h
00030h
00034h
0003Ch
00080h
00084h
DAIBRS
DAIBRDY
DAIBEN
DPRIXB
DINBY
AIB Reset
Read/Write
Read Only
Read/Write
Read/Write
00000003h
00000003h
00000000h
00000000h
00000002h
AIB Ready
AIB Tx Enable
Primary Crossbar Select
Input Bypass Shift Register Depth Read/Write
Output Bypass Shift Register
Read/Write
00088h
DOUTBY
00000002h
Depth
0008Ch
00090h
00094h
00098h
0009Ch
000A0h
DCODEN
DDECEN
DLSRRS
DLSRACT
DPINRS
8B/10B Encoder Enable
Read/Write
Read/Write
Read/Write
Read Only
Read/Write
Read Only
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
8B/10B Decoder Enable
VCSEL Laser Reset (Active-Low)
VCSEL Laser Active Status
PIN Diode Reset (Active-Low)
PIN Diode Signal Detect
DPINDET
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
119
PMC [ PMC-SIERRA, INC ]
