Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Regardless of the Control to iDS information (on p2d_ic), the Credit Information (byte 0 through bit 5 of
byte 4) of the cell header being written on Grant/data to iDS, is saved in a CR (credit register); it is used to
indicate backpressure information back to the linecard. The CRC contained in the LCS header of the frame
coming from the Grant/Data to iDS is computed only over the Tag portion of the LCS header. Another CRC
in the frame that is computed only over the Credit portion of the LCS header is sent to DS0. This credit
CRC is stored in the CR with the credits.
The Control to iDS frame contains a read request and read address. If the read request is asserted, the
iQM location specified by the read address is read and the cell is sent through the Crossbar AIB Interface.
The routing tag carried in the Control to iDS link is placed at the head of the cell as it is sent to the
Crossbar.
If the “SendZero” bit is set, the DS sends an all-zero frame into the Crossbar instead of reading the cell
from the queue memory.
2.1.2.2 Output Side Data Flow
Data cells entering the oDS devices from the Crossbar AIB Interface are placed into the oBypass. For
DS0, DS1, and DS2, the cells are sent to the EPPs via the Data from oDS busses, d2p_d[1:0]_id. The VLD
bit sent to the EPPs is the same as the VLD bit received from the Crossbars.
The EPP, having decided to store this new cell, sends a control frame over the Control to oDS bus, p2d_ic.
This frame contains a write address and write request. If the write request is asserted, the cell at the head
of the oBypass is placed into the oQM location designated by the write address. If the write request is not
asserted, the cell at the head of the oBypass is removed from the FIFO and discarded.
The Control to oDS frame also contains a read request and read address. If the read request is asserted,
then the cell in the oQM location specified by the read address is removed from the memory and placed in
the oFIFO.
If the “SendZero” bit is set, the DS inserts an all-zero frame into the oFIFO instead of reading a cell from
queue memory.
As the cell is inserted into the oFIFO, bytes 0 through the first part of byte 4 (the Credit Information fields of
the LCS header) are overwritten by the contents of the CR (Credit Register) by DS0, and the LCS CRC is
computed as the XOR of the tag CRC contained in the cell and the Credit CRC contained in the CR. If the
Serdes clock rate is slightly less than the core clock rate, this oFIFO occasionally fills up. The EPP can be
programmed to insert one “idle” cell periodically into the stream entering the oFIFO to avoid filling the
oFIFO. The EPP does not assert either a read request or a “send zero” command to the oDS for these
“idle” cells, nor does the oDS insert any cell into the oFIFO. The frequency of these idle cells is
programmable and determined by the relative clock frequencies of the switch core and the linecard.
2.2 8B/10B INTERFACE
The Dataslice connects to the outside world via a 10-bit wide transmit and receive interface. In the ingress
direction, an 8B/10B decoder lookup table maps received 10-bit characters into LCS data bytes. In the
egress direction, an 8B/10B encoder lookup table maps LCS data bytes into 10-bit characters to be
transmitted. The 8B/10B encoder and decoder lookup tables can be programmed to use any arbitrary
8B/10B code.
118
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
