Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
2.1.1 OOB Interface and Control/Status Registers
All of the devices have an OOB interface. This interface allows a single local CPU to control and monitor all
of the devices within a core fabric. Internally, each device provides registers that can be mapped into the
CPU’s address space. These registers are described in more detail in Section 2.3 “Dataslice Registers”.
2.1.2 Dataslice Cell Flow
2.1.2.1 Input Side Data Flow
On the input side, LCS cells are sent to the Dataslice from the Serdes interface and enter the iFIFO. The
header and first four bytes of data enter DSs 0 and 1, the next six bytes of data enter DS2, and the last six
bytes of the data enter DS11, as illustrated in Figure 55. Every cell time, one cell is removed from the iFIFO
and sent to the iBypass. If the Dataslice is DS0, DS1, or DS2, the cell is copied and sent through the
Request/Data from iDS, on d2p_d[1:0]_id, to the EPP. If the iFIFO is empty, the DSs write idle (and non
valid) frames to the EPP and iBypass.
Figure 55. Slicing of a Data Cell into Logical Dataslices
Incoming Cell
DS0 DS1
DS2 DS3
DS4 DS5
DS6 DS7
DS8 DS9
Byte 48-53
DS10 DS11
Byte 60-65
Byte 0-5
Byte 12-17
Byte 24-29
Byte 36-41
Byte 42-47
Byte 6-11
Byte 18-23
Byte 30-35
Byte 54-59
Byte 66-71
NOTE: For more information on Dataslice synchronization, see Section 2.2.1 “Synchronization” on
page 333.
The Control to iDS, p2d_ic, provides the write address and write request. If the write request is valid, the
cell is written to the iQM location specified by the write address. For DS0, DS1, and DS2, the data from
Grant/data to iDS, p2d_d[1:0]_id, is written to memory. For DS3 through DS11, the head cell from the
iBypass is written to memory.
If the write request is not valid, nothing is written to memory. The cell being transferred out of the head of
the iBypass registers is dropped.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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