NSE-8G™ Standard Product Data Sheet
Preliminary
Pin/ Enable
Logic one
Logic one
Logic one
Logic one
Notes
Register Bit
Cell Type
IN_CELL
IN_CELL
IN_CELL
IN_CELL
I.D. Bit
3
2
1
0
-
-
-
-
1. When set high, INTB will be set to high impedance.
2. Enable cell OEB_pinname, tristates pin pinname when set high.
3. OEB_INTB is the first bit of the boundary scan chain.
4. Cells ‘Logic one’ are Input Observation cells whose input pad is bonded to VDD internally.
11.2.1 Boundary Scan Cells
In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is
SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the
diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID
Code bit is as listed in the Boundary Scan Register, Table 14.
Figure 13 Input Observation Cell (IN_CELL)
IDCODE
Scan Chain Out
INPUT
to internal
logic
Input
Pad
G1
G2
SHIFT-DR
1 2
1 2
1 2
1 2
D
MUX
C
I.D. Code bit
CLOCK-DR
Scan Chain In
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
131
PMC [ PMC-SIERRA, INC ]
