NSE-8G™ Standard Product Data Sheet
Preliminary
Register 115h + N*20H, ILC Receive Auxiliary, Status and FIFO Synch Register
Bit
Type
R
R
R
R
R
R
R
Function
Reserved
RX_AUX[7:0]
RX_STTS_VALID
RX_LINK[1:0]
RX_PAGE[1:0]
RX_USER[2:0]
CRC_ERR
Default
00000000
Bit 31:24
Bit 23:16
Bit 15
Bit 14:13
Bit 12:11
Bit 10:8
Bit 7
00h
N/A
00
00
000
0
Bit 6
Bit 5:2
Bit 1
Bit 0
Bit 0
R
R
R
W
R
HDR_CRC_ERR
RX_MSG_LVL[3:0]
RX_FI_BUSY
RX_XFER_SYNC
RX_SYNC_DONE
0
0000
0
N/A
0
This register serves a dual-purpose dependant on whether it is being read or written.
When it is read it returns the status for the Message Receive Channel.
When it is written (with 00000001h) to it is used it synchronize the Receive FIFO to the start of a
message boundary or perform a message skip.
RX_AUX[7:0]
These bits constitute the output from an Auxiliary channel between CPUs at each end of the
link. Their use is at the Software developers’ discretion. A read from this register will return
the AUX header byte of the last message received (without a CRC-16 error).
RX_XFER_SYNC
Rx Transfer sync writing Writing ‘1’ to this bit initiates a read sequence from the start of the
next unread message. The hardware
°
°
Aligns the message read buffer address to the start of the next unread message
Prefetches the 1st Dword from the unread message buffer so that it is ready for a s/w read
from the Receive FIFO Data register(s)
An unread message in this context means that the s/w has not read any of the message
payload data by reading the Receive FIFO Data register(s)
After the RX XFER SYNC process has been completed successive reads from the Receive
FIFO return the last Dword read from the Receive FIFO and prefetch the next Dword (when
available).
This bit must be written to a ‘1’ at the start of a message read sequence.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
117
PMC [ PMC-SIERRA, INC ]
