NSE-8G™ Standard Product Data Sheet
Preliminary
RX_MSG_LVL[3:0]
This indicates the current number of messages in the Receive FIFO.
Table 8 RX FIFO Message Level
RX_MSG_LVL[3:0]
Number of messages
0000
:
0
:
1000
8
Values greater than 1000 will not occur.
HDR_CRC_ERR
If this bit is set to ‘1’, the last message slot received was received with an errored CRC-16
field. This bits is updated every message slot. This bit is provided as status only.
CRC_ERR
If this bit it set to ‘1’, the message at the head of the Receive FIFO has an errored CRC-16
field.
The usual sequence would be to read this register before reading the message buffer to check
if the message buffer that will be read from next has been received with a CRC error. If a
Receive FIFO Synchronization has been started the value of this bit is invalid until the
RX_XFER_SYNC operation has completed. When FAST_RD_EN is a ‘1’ this bit is valid
when RX_FI_BUSY is a ‘0’ following a Receive FIFO Synchronization. When
FAST_RD_EN is a ‘0’ the values of RX_FI_BUSY and CRC_ERR change concurrently and
a further read should be made after RX_FI_BUSY is sampled as a ‘0’ before checking the
value of this bit.
OUSER[2:0]
These bits are a reflection of the OUSER[2:0] bits output from the far end and indicate the
value of the received USER bits in the received message header of the last message received
(without a CRC-16 error). These bits are available in the three top level SBS User bits
registers at a bit position equal to the link number.
OPAGE[1:0]
These bits are a reflection of the OPAGE[1:0] bits output from the far end and indicate the
value of the received PAGE bits in the received message header of the last message received
(without a CRC-16 error). These bits are available in the two top level SBS page bits registers
at a bit position equal to the link number.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
119
PMC [ PMC-SIERRA, INC ]
