PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
8.8.2 Transmit Partial Packet Buffer Processor
The partial packet buffer processor controls the 32 Kbyte partial packet RAM
which is divided into 16 byte blocks. A block pointer RAM is used to chain the
partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous
sections of RAM can be allocated in the partial packet buffer RAM to create a
channel FIFO. Figure 4 shows an example of three blocks (blocks 1, 3, and 200)
linked together to form a 48 byte channel FIFO. The three pointer values would
be written sequentially using indirect block write accesses. When a channel is
provisioned within this FIFO, the state machine can be initialized to point to any
one of the three blocks.
Figure 4 – Partial Packet Buffer Structure
Partial Packet
Buffer RAM
Block
Pointer RAM
16 bytes
16 bytes
16 bytes
16 bytes
XX
0x03
XX
Block 0
Block 1
Block 2
Block 3
Block 0
Block 1
Block 2
Block 3
0xC8
16 bytes
16 bytes
0x01
XX
Block 200
Block 200
Block 2047
Block 2047
The partial packet buffer processor is divided into three sections: reader, writer
and roamer. The roamer is a time-sliced state machine which tracks each
channel’s FIFO buffer free space and signals the writer to service a particular
channel. The writer requests data from the TAPI672 block and transfers packet
data from the TAPI672 to the associated channel FIFO. The reader is a time-
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
