PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
reception (REOP high) to indicate that the packet is in error. The RAPI672 may
optionally be programmed to overwrite RXDATA[7:0] of the final word of each
packet transfer (REOP is high) with the status of packet reception when that
packet is errored (RERR is high). Overwriting of status information is enabled by
setting the STATEN bit in the RAPI Control register.
8.6.2 Polling Control and Management
The RAPI672 only responds to device polls which match the base address
programmed in the RAPI672 Control register. A positive poll response indicates
that at least one of the two FIFOs has a complete XFER[3:0] plus one blocks of
data, or an end of packet, and is ready to be selected to transfer this data across
the Rx APPI.
8.7 Transmit Any-PHY Interface
The Transmit Any-PHY Interface (TAPI672) provides a low latency path for
transferring data from the Transmit Any-PHY Packet Interface (Tx APPI) into the
partial packet buffer in the THDL672. The TAPI672 contains a FIFO block for
latency control as well as to segregate the APPI timing domain from the SYSCLK
timing domain. The TAPI672 contains the necessary logic to manage and respond
to channel polling from an upper layer device.
8.7.1 FIFO Storage and Control
The FIFO block temporarily stores channel data during transfer across the Tx
APPI. TAPI672 burst data transfers are transaction based on the writer side of
the FIFO – all data must be completely read from the FIFO before any further
data will be written into the FIFO. To support as close as possible to full Tx APPI
bus rate, a double buffer is used. While data is being read from the one FIFO,
data can be written into the other FIFO. Because the bandwidth on the reader
side of the FIFOs is higher than that on the writer side, the TAPI672 will not incur
any bandwidth reduction to maximum burst data transfers through its FIFOs.
The upper layer device cannot interrupt data transfers on the Tx APPI. However,
the FREEDM-84A672 may throttle the upper layer device if both FIFOs in the
TAPI672 are full. When the FIFOs in the TAPI672 cannot accept data, the
TAPI672 deasserts the TRDY output to the upper layer device connected to the
Tx APPI. In this instance, the upper layer device must halt data transfer until the
TRDY output is returned high. The upper layer device connected to the Tx APPI
must sample the TRDY output high before continuing to burst data across the Tx
APPI.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
