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PM7385 参数 Datasheet PDF下载

PM7385图片预览
型号: PM7385
PDF下载: 下载PDF文件 查看货源
内容描述: 84 LINK , 672通道帧引擎和数据链路管理与ANY -PHY分组接口 [84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE]
分类和应用:
文件页数/大小: 244 页 / 2231 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7385 FREEDM-84A672  
DATA SHEET  
PMC-1990114  
ISSUE 6  
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER  
WITH ANY-PHY PACKET INTERFACE  
to 28 of each SPE), the TCAS672 provides a single byte holding register. The  
TCAS672 performs parallel to serial conversion to form bit-serial streams which  
are passed to the SBI SIPO blocks. In the event where multiple links are in need  
of data, TCAS672 requests data from upstream blocks on a fixed priority basis  
with link 0 having the highest priority and link 83 the lowest.  
Links containing a T1/J1 or an E1 stream may be channelised. Data at each  
time-slot may be independently assigned to be sourced from a different channel.  
The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse  
signals generated by the SBI SIPO blocks. With knowledge of the transmit link  
and time-slot identity, the TCAS672 performs a table look-up to identify the  
channel from which a data byte is to be sourced.  
Links containing a DS-3 stream are unchannelised, in which case, all data bytes  
on the link belong to one channel. The TCAS672 performs a table look-up to  
identify the channel to which a data byte belongs using only the outgoing link  
identity, as no time-slots are associated with unchannelised links. Links may  
additionally be configured to operate in an unframed “clear channel” mode, in  
which case the FREEDM-84A672 will output HDLC data in all bit positions,  
including those normally reserved for framing information. Links so configured  
operate as unchannelised regardless of link rate and the TCAS672 performs a  
table lookup using only the link number to determine the associated channel.  
8.9.1 Line Interface  
There are 84 line interface blocks in the TCAS672. Each line interface block  
contains a bit counter, an 8-bit shift register and a holding register that, together,  
perform parallel to serial conversion. Whenever the shift register is updated, a  
request for service is sent to the priority encoder block. When acknowledged by  
the priority encoder, the line interface responds by writing the data into the  
holding register.  
To support channelised links, each line interface block contains a time-slot  
counter. The time-slot counter is incremented each time the shift register is  
updated and is reset on detection of a frame pulse from the SBI SIPO blocks.  
For unchannelised or unframed links, the time-slot counter is held reset.  
8.9.2 Priority Encoder  
The priority encoder monitors the line interfaces for requests and synchronises  
them to the SYSCLK timing domain. Requests are serviced on a fixed priority  
scheme where highest to lowest priority is assigned from the line interface  
attached to link 0 to that attached to link 83. Thus, simultaneous requests from  
link ‘m’ will be serviced ahead of link ‘n’, if m < n. The priority encoder selects the  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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