PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
sliced state machine which transfers the HDLC information from a channel FIFO
to the HDLC processor in response to a request from the HDLC processor. If a
buffer under-run occurs for a channel, the reader informs the HDLC processor
and purges the rest of the packet. If a buffer overflow occurs for a channel (this
can only happen if an external device disregards or mis-interprets poll results on
the Tx APPI and transfers data to a channel which does not have space in its
FIFO), the THDL672 overwrites the FIFO contents resulting in data corruption on
that particular channel. When either an underflow or an overflow occurs, an
interrupt is generated and the cause of the interrupt may be read via the interrupt
status register using the microprocessor interface.
The writer and reader determine empty and full FIFO conditions using flags.
Each block in the partial packet buffer has an associated flag. The writer sets the
flag after the block is written and the reader clears the flag after the block is read.
The flags are initialized (cleared) when the block pointers are written using
indirect block writes. The reader declares a channel FIFO under-run whenever it
tries to read data from a block without a set flag.
The FIFO algorithm of the partial packet buffer processor is based on per-
channel software programmable transfer size and free space trigger level.
Instead of tracking the number of full blocks in a channel FIFO, the processor
tracks the number of empty blocks, called free space, as well as the number of
end of packets stored in the FIFO. Recording the number of empty blocks
instead of the number of full blocks reduces the amount of information the
roamer must store in its state RAM.
The partial packet roamer records the FIFO free space and end-of-packet count
for all channel FIFOs. When the reader signals that a block has been read, the
roamer increments the FIFO free space and sets a per-channel request flag if the
free space is greater than the limit set by XFER[3:0]. The roamer pushes this
status information to the TAPI672 to indicate that it can accept at least XFER[3:0]
blocks of data. The roamer also decrements the end-of-packet count when the
reader signals that it has passed an end of a packet to the HDLC processor. If
the HDLC processor is transmitting a packet and the FIFO free space is greater
than the starving trigger level and there are no complete packets within the FIFO
(end-of-packet count equal to zero), a per-channel starving flag is set. The
roamer searches the starving flags in a round-robin fashion to decide which
channel FIFOs are at risk of underflowing and pushes this status information to
the TAPI672. The roamer listens to control information from the TAPI672 to
decide which channel FIFO requests data from the TAPI672 block. The roamer
informs the partial packet writer of the channel FIFO to process and the FIFO
free space. The writer sends a request for data to the TAPI672 block, writes the
response data to the channel FIFO, and sets the block full flags. The writer
reports back to the roamer the number of blocks and end-of-packets transferred.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
54
PMC [ PMC-SIERRA, INC ]
