PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Table 5 – Miscellaneous Interface Signals (111)
Pin Name Type
Pin
No.
Function
SYSCLK
RSTB
Input
Input
L1
The system clock (SYSCLK) provides timing for
the core logic. SYSCLK is nominally a 50% duty
cycle clock of frequency 45 MHz ±50ppm.
E3
The active low reset signal (RSTB) signal
provides an asynchronous FREEDM-84A672
reset. RSTB is an asynchronous input. When
RSTB is set low, all FREEDM-84A672 registers
are forced to their default states. In addition, all
SBI, APPI and µP interface output pins are forced
tristate and will remain tristated until RSTB is set
high.
PMCTEST Input
AE22 The PMC production test enable signal
(PMCTEST) places the FREEDM-84A672 is test
mode. When PMCTEST is set high, production
test vectors can be executed to verify
manufacturing via the test mode interface signals
TA[11:0], TA[12]/TRS, TRDB, TWRB and
TDAT[15:0]. PMCTEST must be tied low for
normal operation.
TCK
TMS
TDI
Input
Input
Input
U4
W1
V3
The test clock signal (TCK) provides timing for
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS and TDI are
sampled on the rising edge of TCK. TDO is
updated on the falling edge of TCK.
The test mode select signal (TMS) controls the
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS is sampled
on the rising edge of TCK. TMS has an integral
pull up resistor.
The test data input signal (TDI) carries test data
into the FREEDM-84A672 via the IEEE P1149.1
test access port. TDI is sampled on the rising
edge of TCK.
TDI has an integral pull up resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
32
PMC [ PMC-SIERRA, INC ]
