PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Table 4 – Microprocessor Interface Signals (31)
Pin Name
Type
Pin
No.
Function
D[0]
I/O
C22
D21
A23
B22
C21
D20
A22
B21
C20
D19
B20
C19
A20
B19
C18
D17
The bi-directional data signals (D[15:0]) provide
a data bus to allow the FREEDM-84A672 device
to interface to an external micro-processor.
Both read and write transactions are supported.
The microprocessor interface is used to
configure and monitor the FREEDM-84A672
device.
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
Input
Input
A19
B18
C17
A18
D16
B17
C16
A17
B16
D15
The address signals (A[11:2]) provide an
address bus to allow the FREEDM-84A672
device to interface to an external micro-
processor. All microprocessor accessible
registers are dword aligned.
ALE
A16
The address latch enable signal (ALE) latches
the A[11:2] signals during the address phase of
a bus transaction. When ALE is set high, the
address latches are transparent. When ALE is
set low, the address latches hold the address
provided on A[11:2].
ALE has an integral pull-up resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
30
PMC [ PMC-SIERRA, INC ]
