PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Table 7 – Power and Ground Signals (64)
Pin Name
Type
Pin
No.
Function
VDD3V3[1]
VDD3V3[2]
VDD3V3[3]
VDD3V3[4]
VDD3V3[5]
VDD3V3[6]
VDD3V3[7]
VDD3V3[8]
VDD3V3[9]
VDD3V3[10]
VDD3V3[11]
VDD3V3[12]
VDD3V3[13]
VDD3V3[14]
VDD3V3[15]
VDD3V3[16]
VDD3V3[17]
VDD3V3[18]
VDD3V3[19]
VDD3V3[20]
VDD3V3[21]
VDD3V3[22]
VDD3V3[23]
VDD3V3[24]
Power
B25
The VDD3V3[24:1] DC power pins should be
connected to a well decoupled +3.3 V DC
supply. These power pins provide DC
current to the I/O pads.
C3
C24
D4
D9
D14
D18
D23
J4
N4
P23
J23
V4
V23
AC4
AC9
AC13
AC18
AC23
AD3
AE2
AE25
B2
AD24
VDD2V5[1]
VDD2V5[2]
VDD2V5[3]
VDD2V5[4]
VDD2V5[5]
VDD2V5[6]
VDD2V5[7]
VDD2V5[8]
VDD2V5[9]
VDD2V5[10]
VDD2V5[11]
VDD2V5[12]
Power
H4
The VDD2V5[12:1] DC power pins should be
connected to a well decoupled +2.5 V DC
supply. These power pins provide DC
current to the digital core.
P4
Y3
AF6
AE14
AF21
AA26
N25
G24
A21
B13
A6
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36
PMC [ PMC-SIERRA, INC ]
